A conventional method for manufacturing a semiconductor wafer includes a slice process for slicing a semiconductor ingot to obtain a wafer, a lapping process for removing a surface flaw and irregularity caused by the slice by lapping a sliced wafer surface or a grinding process for performing one-sided grinding or double-sided grinding to improve flatness, an etching process for etching the wafer by dipping the wafer in acid or alkali so as to remove a processing distortion layer (or processing damage layer) of the wafer surface flattened in the process, and a minor polishing process for polishing the etched wafer.
However, the following problems occur in the processes of the conventional manufacturing method as described above.
Surface grinding used in the grinding or lapping process is advantageous to improve the flatness. However, a subsequent process should eliminate processing distortion since the processing distortion layer increases. Since an increased etching amount is required, the process is time-consuming and therefore productivity is low.
A technique similar to these techniques is disclosed in Japanese Unexamined Patent Application, First Publication No. H11-135464 (Patent Document 1).